Digitally assisted pipelined ADC
Two digital coefficients make a cheap open-loop amplifier good enough for a 12-bit, 100 MS/s pipelined ADC.
Top: linearity error over all output codes. Bottom: output spectrum of a 3.1 MHz sine. The cubic correction fades in and out.
Simulation in gpdk45: transistor-level residue amplifier, behavioural pipeline.
Effective resolution rises from 9.3 to 11.6 of 12 bits; the largest distortion tone drops by 22 dB.
Sep–Oct 2026
Why
A pipelined ADC amplifies the leftover error of each stage, the residue, and passes it on. Conventionally that takes a precise closed-loop amplifier, which needs high gain, high bandwidth and accurate settling, and all of that costs power.
Precise op-amps get harder with every process node: at a 1.2 V supply in 45 nm there is little headroom and little intrinsic gain, while digital logic keeps getting cheaper. Boris Murmann proposed a simple open-loop amplifier whose errors are corrected digitally, and cut the amplifier power by about 62% in his prototype.
How
First identify how the open-loop amplifier bends the signal, then undo it in the digital post-processor with an inverse polynomial:
\[\hat{x} = p_1 \hat{y} + p_2 \hat{y}^3\]ŷ is the digitised amplifier output, x̂ the reconstructed residue.
The two coefficients come straight from characterising the isolated amplifier, and an independent in-circuit calibration confirms them.
On a normal plot the amplifier looks perfectly linear. At 12-bit resolution, its slight curvature is what limits the converter, and the cubic model captures it. The key is fitting the model over the residue range the amplifier actually sees.
What
I designed the residue amplifier, a resistor-loaded differential pair, at transistor level in Cadence Virtuoso (gpdk45), and modelled the rest of the pipeline and the digital post-processor in Verilog-A.
The amplifier runs on 105 µW, or 1.05 pJ per conversion at 100 MS/s.
A logger feeds every simulation into Python, where I characterise the amplifier, fit the correction, and verify the converter with ramp and sine tests.
Software: Cadence Virtuoso · Spectre · Verilog-A · Python
Results
| Correction | Peak INL [LSB] | SNDR [dB] | SFDR [dB] | ENOB [bit] |
|---|---|---|---|---|
| Gain only | 3.80 | 57.8 | 71.1 | 9.30 |
| Gain + cubic, fitted over the wrong range (±200 mV) | 1.61 | 61.7 | 72.2 | 9.95 |
| Gain + cubic | 0.23 | 71.8 | 93.4 | 11.63 |
| Ideal 12-bit quantiser (same test) | 0.01 | 73.1 | 94.3 | 11.85 |
INL from a slow ramp; SNDR, SFDR and ENOB from a 3.1 MHz sine at −1 dBFS.
Gain + cubic brings the converter within 1.3 dB of an ideal 12-bit quantiser.
What I learned
- Fit the model over the range you actually use. A fit over a wider range looked excellent and still cost most of the gain.
- Keep calibration and test runs identical. A stale data file from an older run looked exactly like a circuit effect. Running both tests as corners of one setup removed it.
- Pipelines have latency. Without a one-cycle alignment, every stage-1 transition produced a spike of about 256 codes.
Next steps
- Power sweep: SNDR against amplifier power, and an estimate of the closed-loop stage this one replaces.
- Realistic back-end load: add sampling capacitance and check settling and calibration.
- Background calibration: track the coefficients during normal operation instead of using a known ramp.
All details, derivations and the full development log are in the technical report on GitHub.
References
- B. Murmann, “Digitally Assisted Analog Circuits,” Hot Chips 17, 2005. Slides
- B. Murmann and B. E. Boser, “A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification,” IEEE Journal of Solid-State Circuits, vol. 38, no. 12, pp. 2040–2050, Dec. 2003, doi: 10.1109/JSSC.2003.819167.
- A. Sidun, ideal N-bit ADC Verilog-A model: AnalogHub